A phase-locked loop, or PLL, is a control system that is widely employed in telecommunications technology as well as measurement and control systems as frequency sources, to demodulate frequency- or phase-modulated signals, and for clock synchronization and recovery. This novel PLL circuit from Paderborn University is vastly less complex than conventional PLLs with a separate “loss of lock” circuit, meaning it also consumes less power. The best part about the circuit is that it continuously uses a slow sine wave. This type of sine wave is usually only used when a loss of lock has occurred, where a separate circuit is then required. Although the use of a sine wave produces a minor phase difference, it is inconsequential compared to other noise sources. This invention adjusts the continuous sine wave via the phase detector's output signals. Specifically, the electronic circuit consists of a charge pump and a low-pass filter as shown in the figure below. It also contains three current mirrors, charging the capacity based on the DN/UP C inputs in order to compensate for phase differences in a PLL while also applying a continuous sine wave to the upper current mirrors (los,n and los,p) that is slower compared to the oscillator frequency and with which the PLL can be recaptured in case of a loss of lock.