The invention pertains to an integrate-and-hold circuit which is used as a sampler. The typical structure of an integrate-and-hold circuit (IHC) is a multiplier serving as a switch followed by a resettable integrator with a hold capacitor. For a desired signal-to-noise ratio and signal swing the value of the hold capacitor has a minimum acceptable value which always limits the bandwidth.
Many advanced IHC circuit topologies utilize a delayed version of the integrate command signal to derive a track command fed to the switch control. The delay avoids switching noise at the beginning of the tracking. Moreover a tunable delay time facilitates bandwidth adjustment and, hence, SNR adjustment. However, the tunable delay line has a minimum delay, which – again – limits the achievable bandwidth.
It was the aim of scientists of Paderborn University to decouple the sampler bandwidth from the choice of hold capacitance value and to allow for very high bandwidth which in addition should be tunable.